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rej03d0911-0402 rev.4.02 page 1 of 10 apr 01, 2010 preliminary datasheet RNA51953A, b voltage detecting, system resetting ic series description RNA51953A,b are semiconductor integrated circuits designed for detecting supply voltage and resetting all types of logic circuits such as cpus. they include a built-in delay circuit to provide the desired retardation time simply by adding an external capacitor. they fined extensive applications, including battery checking circuit, level detecting circuit and waveform shaping circuit. features ? few external parts ? large delay time with a capac itor of small capacitance (td ? 100 ms, at 0.33 ? f) ? low threshold operating voltage (supply voltage to keep low-state at low supply voltage): 0.6 v (typ) at rl = 22 k ? ? wide supply voltage range: 2 v to 17 v ? wide application range ? ordering information part name package type package code package abbreviation taping abbreviation (quantity) surface treatment RNA51953Afph0 sop-8 pin prsp0008de-c fp h (2,500 pcs / reel) 0 (ni/pd/au) RNA51953Apt0 dip-8 pin prdp0008af-b p t (1,000 pcs / reel) 0 (ni/pd/au) rna51953bfph0 sop-8 pin prsp0008de-c fp h (2,500 pcs / reel) 0 (ni/pd/au) rna51953bpt0 dip-8 pin prdp0008af-b p t (1,000 pcs / reel) 0 (ni/pd/au) application ? reset circuit of pch, nch, cmos, microcomputer, cpu and mcu, reset of logic circuit, battery check circuit, switching circuit back-up voltage, leve l detecting circuit, waveform shapin g circuit, delay waveform generating circuit, dc/dc converter, over voltage protection circuit recommended operating condition ? supply voltage range: 2 v to 17 v rej03d0911-0402 rev.4.02 apr 01, 2010
RNA51953A, b preliminary rej03d0911-0402 rev.4.02 page 2 of 10 apr 01, 2010 outline and article indication trace code ? RNA51953A, b pin no.1 y: year code (the last digit of year) m: month code w: week code c: control code lot no. part no. r 9 5 3 a ymwc ccc sop-8 dip-8 r 9 5 3 b ymwc ccc part no. y: year code m: month code w: week code 55 19 3b r 55 19 3a r y m wy m w pin arrangement 8 5 6 7 nc delay capacito r output power-supply nc gnd nc nc 1 4 3 2 nc: no connection RNA51953A, b (top view) outline: prsp0008de-c (sop-8) prdp0008af-b (dip-8)
RNA51953A, b preliminary rej03d0911-0402 rev.4.02 page 3 of 10 apr 01, 2010 block diagram gnd output delay capacitor ? + ? 1.25 v r1 r2 25 a typ 5 a typ a: built-in load b: open collector RNA51953A, b power- supply operating waveform RNA51953A, b output undefined 4.25 v 0.65 v supply voltage output state h l t t td 0.34 cd(pf) s td td
RNA51953A, b preliminary rej03d0911-0402 rev.4.02 page 4 of 10 apr 01, 2010 absolute maximum ratings (ta = 25c, unless otherwise noted) item symbol ratings unit conditions supply voltage v cc 18 v output sink current isink 6 ma v cc type a (output with constant current load) output voltage v o 18 v type b (open collector output) 400 8-pin sop (prsp0008de-c) power dissipation pd 570 mw 8-pin dip (prdp0008af-b) 4.4 8-pin sop (prsp0008de-c) thermal derating k ? 8.3 mw/c 8-pin dip (prdp0008af-b) refer to the thermal derating curve. operating temperature topr ?40 to +85 c storage temperature tstg ?55 to +125 c electrical characteristics (ta = 25c, unless otherwise noted) ? ?l? reset type item symbol min typ max unit test conditions detecting voltage v s 4.05 4.25 4.45 v hysteresis voltage ? v s 30 50 80 mv detecting voltage temperature coefficient v s /? t ? 0.01 ? %/c ? 450 680 type a , v cc = 5v circuit current i cc ? 420 630 ? a type b , v cc = 5v delay time t pd 1.6 3.4 7.0 ms cd = 0.01 ? f * constant current ipd ?8 ?5 ?3 ? a v cc = 5v output saturation voltage vsat ? 0.2 0.4 v v cc = 4v, isink = 4ma ? 0.67 0.8 r l = 2.2k ? , vsat ? 0.4v threshold operating voltage v opl ? 0.55 0.7 v r l = 100k ? , vsat ? 0.4v output leakage current i oh ? ? 30 na type b output load current i oc ?40 ?25 ?17 ? a type a , v cc = 5v, v o = 1/2 ? v cc output high voltage v oh v cc ?0.2 v cc ?0.06 ? v type a note: please set the desired delay time by atta ching capacitor of the range between 4700 pf and 10 ? f.
RNA51953A, b preliminary rej03d0911-0402 rev.4.02 page 5 of 10 apr 01, 2010 typical characteristics ambient temperature ta (c) 4.34 4.22 ?40 0?20 20 40 8060 100 4.24 4.26 4.28 4.30 4.32 v sh v sl delay time t pd (ms) 0.1 3 5 7 3 5 7 357 110 7 35 100 1000 ambient temperature ta (c) ?40 0?20 20 40 8060 100 canstant current at cd pin ipd (a) ?12 0 ?4 ?8 ?6 ?2 ?10 v cc = 5 v v cc = 15 v supply voltage v cc (v) output voltage v out (v) 1.0 0 0 0.2 0.4 0.6 0.8 1.0 0.2 0.4 0.6 0.8 ta = 25c r l = 2.2 k r l = 22 k r l = 100 k delay capacitance cd ( f) 10 7 5 3 7 5 3 7 5 3 7 5 3 0.001 0.1 0.01 1 v cc = 5 v ambient temperature ta (c) ?40 0?20 20 40 8060 100 delay time t pd (ms) 6 0 3 2 1 5 4 v cc = 5 v 10 v v cc = 15 v c d = 0.01 f detection voltage v s (v) detection voltage vs. ambient temperature threshold operating voltage delay capacitance vs. delay time delay time vs. ambient temperature canstant current at cd pin vs. ambient temperature 600 500 0 0255075 85 100 125 100 200 300 400 thermal derating ambient temperature ta (c) power dissipation pd (mw) 8-pin sop (prsp0008de-c) 8-pin dip (prdp0008af-b)
RNA51953A, b preliminary rej03d0911-0402 rev.4.02 page 6 of 10 apr 01, 2010 output sink current isink (ma) output saturation voltage vsat (v) 0.3 0 02 1 3456 0.1 0.2 v cc = 5 v v cc = 15 v v cc = 10 v output load current vs. output voltage (RNA51953A) output voltage v o (v) output load current i cc (a) 0 0 4 8 12 16 ?10 ?20 ?30 ?40 ambient temperature ta (c) ?40 0?20 20 40 80 60 100 v cc = 5 v circuit current vs. ambient temperature (rna51953b) circuit current i cc (a) 700 0 300 200 100 500 400 600 output saturation voltage vs. output sink current v cc = 4 v
RNA51953A, b preliminary rej03d0911-0402 rev.4.02 page 7 of 10 apr 01, 2010 example of application circuit reset circuit of rna51953 r l v cc rna51953x reset logic circuit gnd delay capacitor gnd cd power- supply power- supply output figure 1 reset circuit of rna51953 notes: 1. when the voltage is anything except 4.25 v, rna5 1957 and rna51958 are used. in this case, the detecting supply voltage is 1.25 ? (r 1 +r 2 )/r 2 (v) approximately. the detecting supply voltage can be set between 2 v and 15 v. 2. the delay time is about 0.34 ? cd (pf) ? s. 3. if the rna51953 and the logic circuit share a common power source, type a (built-in load type) can be used whether a pull-up resistor is included in the logic circuit or not. 4. the logic circuit preferably should not have a pull-down resistor, but if one is present, add load resistor r l to overcome the pull-down resistor. 5. when the reset terminal in the logic circuit is of the low reset type, rna51953 and rna51957 are used and when the terminal is of the high reset type, rna51958 are used. 6. when a negative supply voltage is used, the supply voltage side of rna51953 and the gnd side are connected to negative suppl y voltage respectively. case of using reset signal except supply voltage in the rna51953 out put r l v cc rna51953x rna51953x (a) reset at on reset logic circuit out put gnd delay capacitor gnd cd r l v cc (b) reset at transistor on reset logic circuit gnd delay capacitor gnd cd control signal power- supply power- supply power- supply power- supply figure 2 case of using reset signal except supply voltage in the rna51953
RNA51953A, b preliminary rej03d0911-0402 rev.4.02 page 8 of 10 apr 01, 2010 notice for use about the power supply line 1. about bypass capacitor because the ripple and the spike of the high frequency noise and the low frequency are superimposed to the power supply line, it is necessary to remove these. therefore, please install c 1 and c 2 for the low frequency and for the high frequency between the power supply line and the gnd line as shown in following figure 3. power-supply output v cc rna51953 gnd c 2 c 1 + delay capacito r cd example of ripple noise measures figure 3 example of ripple noise measures setting of delay capacity please use capacitor cd for the delay within the range of 10 ? f or less . when a value that is bigger than this is set, the proble m such as following (1), (2), and (3) becomes remarkable. t v cc output tpd t phl figure 4 time chart at momentary voltage-decrease (1) the difference at delay time becomes remarkable. a long delay setting of tens of seconds is fundamentally possible. however, when set delay time is lengthened, the range of the difference relatively grows, too. when a set value is assumed to be ?tpd?, the difference occurs in the range from 0.47 ? tpd to 2.05 ? tpd. for instance, 34 sec onds can be calculated at 100 ? f. however, it is likely to vary within the ranges of 16-70 seconds. (2) difficulty to react to a momentary voltage decrease. for example, the reaction time t phl is 10 ? s when delay capacitor cd = 0.1 ? f. the momentary voltage-decrease th at is longer than such t phl are occurs, the detection becomes possible. when the delay capacitance is enlarged, t phl also becomes long. for instan ce, it becomes about 100 to 200 ? s in case of circuit constant c1 = 100 ? f. (characteristic graph 1 is used and extrapolation in case of cd = 100 ? f.) therefore, it doesn't react to momentary voltage-decrease th at is shorter than this. (3) original delay time is not obtained. when the momentary voltage-decrease time ?t? is equivalent to t phl , the discharge becomes insufficient and the charge starts at that state. this phenomenon occurs at larg e capacitance. and, original delay time tpd is not obtained. please refer to characteristic graph 2. (d elay time versus input pulse width)
RNA51953A, b preliminary rej03d0911-0402 rev.4.02 page 9 of 10 apr 01, 2010 0.01 0.1 1 delay capacitance cd ( f) 10 100 1000 1 10 100 200 1 10 100 pulse width ( s) characteristic graph 2 delay time vs. momentary voltage decrease pulse width (example data) characteristic graph 1 reaction time vs. delay capacitance (example data) delay time tpd (ms) reaction time t phl ( s) 1000 10000 10000 1000 100 10 1 0.01 f delay capacitance 0.033 f 0.1 f 0.33 f 1 f 2.2 f 3.3 f figure 5 characteristic graph setting of output load resistance (rna51953b) high level output voltage can be set without depending on the power-supply voltage because the output terminal is an open collector type. however, please guard the following notes. 1. please set it in value (2 v to 17 v) within th e range of the power-supply voltage recommendation. moreover, please never impress the voltage of maximum ratings 18 v or more even momentarily either. 2. please set output load resi stance (pull-up resistance) r l so that the output current (output inflow current i l ) at l level may become 4 ma or less. moreover, pleas e never exceed absolute maximum rating (6 ma). v cc (2 v to 17 v) i l 4 ma 6 r l figure 6 output load resistance r l others 1. notes when ic is handled are published in our reliability handbook, and please refer it. the reliability handbook can be downloaded from our homepage (following url). http://www.renesas.com/products/comm on_info/reliability/reliability_root.jsp 2. additionally, please inquire of our company when there is an uncertain point on use.
RNA51953A, b preliminary rej03d0911-0402 rev.4.02 page 10 of 10 apr 01, 2010 package dimensions a l e c 1 b 1 d e a 2 b p c x y h e z l 1 4.854.65 0.90 0.12 0 8 6.2 0.15 0.20 0.25 1.12 1.42 0.46 0.00 0.1 0.20 4.4 1.85 4.6 4.2 0.25 0.45 0.65 2.03 reference symbol dimension in millimeters min nom max 5.05 a 1 0.34 0.4 6.5 5.7 1.27 0.10 0.75 5 8 4 f *1 *2 *3 p mx y 1 index mark e a z b e h d p terminal cross section ( ni/pd/au plating ) c b 1 detail f a 2 a note) 1. dimensions"*1 (nom)"and"*2" do not include mold flash. 2. dimension"*3"does not include trim offset. e p-sop8-4.4x4.85-1.27 0.1g mass[typ.] ? prsp0008de-c renesas code jeita package code previous code 1 l l ( ni/pd/au plating ) 5 8 4 1 3 1 p 1 e d e b b a la e z c 0.89 2.54 1.27 0.480.40 7.4 10.6 15 0 2.792.542.29 0.31 0.250.19 1.30 0.56 0.5 e 1 l e c b p a e d b 3 z a 1 5.06 6.30 9.60 reference symbol dimension in millimeters min nom max 7.62 p-dip8-6.3x9.6-2.54 0.54g mass[typ.] dp-8fv prdp0008af-b renesas code jeita package code previous code
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